An active-pixel sensor (APS) is an image sensor consisting of an integrated circuit containing an array of pixel sensors, each pixel containing a photodetector and an active amplifier. The CMOS APS are used most commonly in cell phone cameras, web cameras and in some Digital single-lens reflex (DSLR) cameras. Such an image sensor is produced by a CMOS process (and also known as a CMOS sensor or CIS).
A Self-Aligned Silicide (salicide) process is a process in which silicide contacts are formed only in those areas in which deposited metal (which becomes a metal component of the silicide after annealing) is in direct contact with silicon, hence, are self-aligned. This process is implemented in MOS/CMOS processes in which ohmic contacts to the source, drain, and poly-Si gate are formed.
The salicide process begins with deposition of a thin transition metal layer over fully formed and patterned semiconductor devices (e.g., transistors). The wafer is heated, allowing the transition metal to react with exposed silicon in the active regions of the semiconductor device (e.g., source, drain, gate) forming a low-resistance transition metal silicide. The transition metal does not react with the silicon oxide and/or nitride insulators present on the wafer. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in only the active regions of the device.
Currently many CIS processes use a silicide process at the poly gate only, but not at the pixel contact. The CIS pixel contact produced without a silicide process can result in very high pixel contact resistance of more than 1000 ohm/sq, especially with the advanced technology, i.e., when the physical dimension of the CIS process technology shrinks gradually (e.g., 65 nm, 45 nm, etc.).
Also, the advanced technology will face a short channel effect (SCE) that induces a leakage concern. Short channel effect arises as the channel length L is reduced to increase both the operation speed and the number of components per chip. The short-channel effects are attributed to two physical phenomena: (1) the limitation imposed on electron drift characteristics in the channel, and (2) the modification of the threshold voltage due to the shortening channel length.
Because of SCE induced leakage, new silicide materials (e.g., Ni, Ta, Yb, Pt, or any other suitable materials and/or combinations thereof) can be possibly used for different NMOS or PMOS. For example, the current process technology for less than 65 nm resolution is a SiGe process for PMOS, which is different from an NMOS process. Therefore, contact etching will face a selective capability issue. The CIS contact-etching process needs to stop on Silicide and Si film, the two films with different etch rates. This stoppage is a challenge for the etching process of advanced technology, especially with 65 nm or less resolution. The selective capability issue can lead to an open pixel contact, i.e., a contact hole having no contact with the source or drain of CMOS devices.
Accordingly, new methods and processes for CIS are desired to reduce pixel contact resistance and to prevent high leakage and open contacts.